Next Generation On-chip Communication Networks

Project Goal: Due to the constraints of VLSI scaling, future processor and system-on-chip designs will by necessity incorporate on-chip communication networks. In the project, we plan to investigate protocols and signalling technologies in the context of future on-chip multiprocessors in the 50nm regime. In this regime, interconnect delay becomes a major challenge and needs to be taken into account at all levels. This will require predicting scaling trends for devices and interconnect, and based on these models designing protocols and circuits. Our main design goal is minimum energy delay product.